Compared to PCs, annealing processors use less energy and solve mathematical optimization problems more quickly. A novel method for creating scalable fully coupled annealing processors has now been developed by researchers at Tokyo University of Science. These quantum-inspired systems can simulate magnetic spin interactions and use them to tackle challenging optimization issues. The new method works much better than current CPUs and could be used in areas like artificial intelligence, materials science, and finding new drugs.
Have you ever had to choose the best option from a plethora of alternatives, such as choosing the quickest route to a specific location while taking traffic and travel time into account? If that’s the case, the issue you were facing is formally referred to as a “combinatorial optimization problem.” Even though these problems are expressed mathematically, they come up in many real-world situations, such as logistics, network routing, machine learning, and materials science.
However, solving large-scale combinatorial optimization problems with conventional computers requires a significant amount of computational power, which forces researchers to use alternative strategies. The “Ising model,” which uses mathematics to represent the magnetic orientation of atoms, or “spins,” in a ferromagnetic material, is one such strategy. These atomic spins are randomly oriented at high temperatures. The spins align, however, to reach the minimum energy state where each spin’s orientation is dependent on its neighbors, as the temperature drops. It turns out that this “annealing” procedure can be used to simulate combinatorial optimization issues in such a way that the final state of the spins produces the best result.
Researchers have attempted to develop semiconductor devices using large-scale integration (LSI) technology in an effort to mimic the behavior of spins by annealing processors that use quantum devices. In particular, the research team led by Professor Takayuki Kawahara at Tokyo University of Science (TUS) in Japan has made significant strides in this area.
One of the first fully coupled (that is, accounting for all possible spin-spin interactions instead of interactions with only neighboring spins) LSI annealing processors, consisting of 512 fully-connected spins, was presented by Prof. Kawahara and his colleagues at the 2020 international conference, IEEE SAMI 2020. The journal IEEE Transactions on Circuits and Systems I: Regular Papers published their work. Due to the enormous number of connections between spins that must be taken into account, these systems are notoriously challenging to implement and scale up. Scalability could have been fixed by running several fully connected chips in parallel, but this would have required an unreasonable number of connections (wires) between chips.
A clever solution to this issue was presented by Prof. Kawahara and his colleagues in a recent study that was published in Microprocessors and Microsystems. They created a novel technique where the energy state calculation of the system is first split among numerous fully coupled chips, forming an “array calculator.” The results from the remaining chips are then combined and computed by a second type of chip known as a “control chip,” which is used to update the values of the simulated spins. According to Prof. Kawahara, “the benefit of our approach is that the amount of data transmitted between the chips is extremely small.” Despite the fact that its fundamentals are straightforward, this approach enables us to realize a scalable, fully connected LSI system for solving combinatorial optimization problems via simulated annealing.
Using widely used programmable semiconductor devices known as commercial FPGA chips, the researchers successfully put their strategy into practice. They created a fully connected annealing system with 384 spins and used it to address a number of optimization issues, such as the 384-node maximum cut problem and the 92-node graph coloring problem. Most importantly, these proof-of-concept tests demonstrated that the suggested method actually improves performance. When solving the maximum cut problem, the FPGA implementation was 584 times faster and 46 times more energy efficient than a typical modern CPU modeling the same annealing system.
The researchers intend to advance their method now that the basic principles of its operation have been successfully demonstrated on an FPGA. Prof. Kawahara states, “To increase the capacity and significantly enhance the performance and power efficiency of our method, we wish to produce a custom-designed LSI chip.” This will help us get the performance we need in areas like drug discovery and material development, which both involve very hard optimization problems.
Prof. Kawahara concludes by saying that he wants to encourage the application of their findings to resolve actual societal issues. His team aspires to conduct collaborative research with businesses and apply their methodology to the fundamentals of semiconductor design technology, paving the way for the resurgence of semiconductors in Japan.
